The invention relates in general to the synchronization of a digital data stream with a given clock signal. In particular the invention relates to synchronization in a situation where the data signal to be synchronized involves a clock signal which is not the same as the clock signal with which the data stream is to be synchronized.
Many digital apparatuses process data streams, or chronological sequences of successive states. A data stream may be one bit wide, in which case its state is represented by bit value 0 or 1, or it may be N bits wide, where N is a positive integer, in which case the state has 2N possible values. When we say that a data stream is synchronized, we mean that the changes between the successive states take place in a given fixed relation to a certain clock signal. We can, for example, specify that the clock signal is a regular square pulse, in which case a change between two successive states is allowed only on the rising and/or falling edge of the clock signal. The term rising edge means a change in the clock signal from logical state 0 into logical state 1, and, conversely, the term falling edge means a change from logical state 1 into logical state 0.
Problems arise in a situation in which a data stream is synchronized with its own clock signal but said data stream should also be processed in an apparatus or part of an apparatus controlled by another clock signal. Two different clock signals are hardly ever in synchronization with each other but they both may have momentarily varying frequencies, pulse ratios and phases. Thus, a data stream synchronized with one clock signal is not constantly synchronized with another clock signal, which may cause errors in the processing of the data signal.
An object of the present invention is to provide a method and an apparatus with which a data stream synchronized with a first clock signal can be transformed such that it is synchronized with a second clock signal.
This and other objects of the invention are achieved by writing the states of the data stream in synchronization with a first clock signal consecutively into latches which are read in synchronization with a second clock signal so that the validity of the states read is checked in conjunction with the reading of the latches.
The method according to the invention is characterized in that
successive states of a data stream are written cyclically in synchronization with a first clock signal into parallel storage units,
states written into the parallel storage units are read cyclically in synchronization with a second clock signal, and
it is indicated whether the state read from a given storage unit is valid or not.
The invention also concerns an electronic apparatus which is characterized in that it comprises
a plurality of parallel latches,
means for writing successive states of the data stream in synchronization with a first clock signal into parallel latches,
means for cyclically reading the states written into the parallel latches in synchronization with a second clock signal, and
means for indicating the validity of a state read from a given latch.
According to the invention, it is formed a synchronizing element comprised of parallel latches into which the data stream to be synchronized is directed. There are at least two parallel latches, but there may also be more of them. The successive states of the data stream are written cyclically into the latches in synchronization with a first clock signal such that a certain first state is written into the first latch, a is following second state is written into the second latch and so forth until the state following the state written into the last latch is again written into the first latch. In conjunction with writing it is stored an indication that the latch contains an unread state.
States stored in the latches are read cyclically in synchronization with a second clock signal. In conjunction with the reading it is checked if the state in the latch has already been read. If it has been read, it will not be read anew but will be indicated erroneous. The successive states read without errors form a data stream synchronized with the second clock signal. When a state stored in a particular latch has been read once, an indication of this is stored lest the same state be read again.